Modulation apparatus and method, and dsv-control-bit generating method

ABSTRACT

A modulation apparatus and method for more accurately determining a value of a control bit to be inserted into a data sequence and digital sum value (DSV) control bit generating method in which a data conversion unit supplies modulation-delimiter information including information regarding delimiters of modulation of a data sequence based on a conversion table to a modulation-delimiter detecting unit and supplies to a valid-delimiter detecting unit a DSV-segment-delimiter signal including information regarding a delimiter position of a DSV segment of the data sequence having the DSV control bit. The modulation-delimiter detecting unit detects modulation-delimiter positions based on the modulation-delimiter information supplied thereto and supplies a modulation-delimiter signal to the valid-delimiter detecting unit. The valid-delimiter detecting unit, based on the DSV-segment-delimiter signal supplied thereto, detects a valid-delimiter position for controlling timing for determining a DSV control bit of the relevant DSV segment from the modulation-delimiter positions represented by the modulation-delimiter signal supplied thereto.

TECHNICAL FIELD

The present invention relates to modulation apparatuses and methods, andDSV-control-bit generating methods. Particularly, the present inventionrelates to a modulation apparatus and method and a DSV-control-bitgenerating method that are suitable for use in data transmission orrecording of data on a recording medium.

BACKGROUND ART

When data is transmitted over a particular transmission path or recordedon a recording medium such as a magnetic disc, and optical disc, or amagneto-optical disc, the data is modulated in accordance with thetransmission path or the recording medium.

A known method of such modulation is block coding. In block coding, adata sequence is divided into blocks of a unit consisting of m×i bits(hereinafter referred to as data words), and the data words areconverted into codewords consisting of n×i bits according to anappropriate coding rule. The code is a fixed-length code if i=1, whilethe code is a variable-length code if a plurality of values can beselected as i, that is, if a particular i within a range of 1 to imax (amaximum i) is selected for conversion. The block codes are denoted asvariable-length codes (d, k; m, n; r).

i is referred to as a constraint length, and imax is r (a maximumconstraint length). d denotes a minimum number of successive “0”sbetween successive “1”s, for example, a minimum run of “0”s. k denotes amaximum number of successive “0”s between successive “1”s, for example,a maximum run of “0”s.

When a variable-length code obtained in the manner described above isrecorded on an optical disc, a magneto-optical disc, or the like, forexample, in the case of a compact disc or a mini disc, thevariable-length code is NRZI (non return to zero inverted) modulatedwith “1” represented by inversion and “0” represented by no inversion,and recording is performed based on the NRZI-modulated variable-lengthcode (hereinafter also referred to as a recording waveform sequence). Inan earlier type of magneto-optical disc conforming to an ISO(International Organization for Standardization) standard, whoserecording density is not so high, a bit sequence modulated for recordinghas been directly recorded without undergoing NRZI modulation.

Let a minimum inversion interval of a recording waveform sequence bedenoted as Tmin and a maximum inversion interval thereof as Tmax. Inorder to allow recording at a high density in the direction of linearvelocity, desirably, the minimum inversion interval Tmin is long; thatis, the minimum run d is large. Furthermore, from the perspective ofclock playback, desirably, the maximum inversion interval Tmax is short;that is, the maximum run k is small. Various modulation methods havebeen proposed in order to satisfy these conditions.

More specifically, modulation methods that have been proposed or thatare actually used, for example, in optical discs, magnetic discs,magneto-optical discs, or the like, include RLL(1-7) (also denoted as(1, 7; m, n; r)) and RLL (2-7) (also denoted as (2, 7; m, n; r)), whichare variable-length codes, and fixed-length RLL(1-7) (also denoted as(1, 7; m, n; 1)) that is used for MOs conforming to an ISO standard.

In disk apparatuses that are currently being developed forhigh-recording-density discs such as optical discs or magneto-opticaldiscs, an RLL code (run length limited code) with a minimum run d=1 isoften used.

A conversion table for the variable-length RLL(1-7) code is, forexample, as follows: TABLE 1 RLL (1.7; 2.3; 2) Data Code i = 1 11 00x 10010 01 10x i = 2 0011 000 00x 0010 000 010 0001 100 00x 0000 100 010

The symbol x in the conversion table is considered as “1” if thesubsequent channel bit is “0” and as “0” if the subsequent channel bitis “1”. The maximum constraint length r is two.

Parameters of the variable-length RLL(1-7) is (1, 7; 2, 3; 2). Let a bitinterval of a recording waveform sequence be denoted as T. Then, theminimum inversion interval Tmin expressed by (d+1)T is 2(=1+1)T. Let abit interval of a data sequence be denoted as Tdata. Then, the minimuminversion interval Tmin expressed by (m/n)×2 is 1.33(=(2/3)×2)Tdata.Furthermore, the maximum inversion interval Tmax expressed by (k+1)T is8(=7+1)T ((=(m/n)×8Tdata=(2/3)×8Tdata=5.33Tdata). Furthermore, adetection-window width Tw is expressed by (m/n)×Tdata, and a valuethereof is 0.67(=2/3)Tdata.

In channel-bit sequences obtained by the RLL(1-7) modulation in Table 1,2T, which corresponds to Tmin, has a highest frequency of occurrence,followed by 3T and 4T. The rapid cycle of occurrence of edge informationsuch as 2T and 3T is usually advantageous for clock playback.

However, as the recording density in the direction of linear velocity isfurther increased, conversely, Tmin becomes problematic. That is, whenthe minimum run 2T occurs successively, the recording waveform tends tobe distorted. This is because the recording waveform is subject to theeffect of noise, defocus, tangential tilt, etc. since the waveformoutput for 2T is smaller than other waveform outputs.

As described above, in recording at a high linear density, successiverecording of Tmin (2T) is susceptible to external disturbance such asnoise, and thus an error tends to occur during data playback. A patternof error in data playback in this case is typically such that the edgesbetween the beginning and the end of the successive occurrences of Tmin(2T) are all shifted to cause an error; that is, the length of biterrors generated is long.

When data is recorded on a recording medium or when data is transmitted,code modulation in accordance with the recording medium or atransmission path is executed. If the modulated codes include a DCcomponent, fluctuation tends to arise in various error signals such asan error signal representing a tracking error in controlling a servo ofa disc apparatus, or jitter tends to occur. Thus, it is desired that aDC component be minimized in the modulated codes.

Accordingly, controlling of a DSV (digital sum value) has been proposed.The DSV is a sum obtained by NRZI-modulating (i.e., level coding) achannel-bit sequence and adding up the codes of the bit sequence (datasymbols) considering “1” as ‘+1’ and “0” as ‘−1’. Minimizing theabsolute value of the DSV indicating a DC component of the codesequence, i.e., controlling the DSV, serves to suppress the DC componentof the code sequence.

In the modulated codes based on the variable-length RLL(1-7) table shownin Table 1 given earlier, DSV control is not executed. In such a case,DSV control is implemented by calculating DSVs at a predeterminedinterval in a modulated code sequence (channel-bit sequence) andinserting predetermined DSV controls bit into the code sequence(channel-bit sequence).

However, the DSV control bits are basically redundant bits. Thus, fromthe viewpoint of the efficiency of code conversion, the number of DSVcontrol bits should be minimized.

Furthermore, it is desired that a minimum run d and a maximum run k donot change depending on DSV control bits that are inserted. This isbecause recording and playback characteristics are affected if (d, k)changes.

In actual RLL codes, however, although the minimum run must be compliedwith, the maximum run need not necessarily be complied with. In someformats, a pattern that does not comply with the maximum run is used asa synchronization signal. For example, although 8-16 code for DVDs(digital versatile discs) have a maximum run of 11T, 14T, which exceedsthe maximum run, is used in a synchronization signal pattern to improvethe detectability of the synchronization signal.

Thus, in the RLL(1-7) code, which exhibits a favorable conversionefficiency, in accordance with increase in density, it is important tocontrol successive occurrences of the minimum run more suitably inaccordance with a high linear density and to exercise DSV control asefficiently as possible.

For example, Japanese Unexamined Patent Application Publication No.11-177431, filed earlier by the applicant of this application, disclosesa modulation apparatus including DSV-control-bit inserting means forgenerating a first data sequence by inserting a first DSV control bit ina data sequence and for generating a second data sequence by inserting asecond DSV control bit in the data sequence; modulation means formodulating both the first data sequence and the second data sequenceusing a conversion table such that the number of “1”s in an element ofdata sequences and the number of “1”s in a corresponding element ofcodeword sequences are coincidentally one or zero modulo two; and DSVcalculating means for calculating a first segment DSV of the first datasequence having been modulated based on the conversion table and asecond segment DSV of the second data sequence having been modulatedbased on the conversion table, and based on values obtained by addingthese DSVs to an accumulated DSV, selecting and outputting one of thefirst data sequence and the second data sequence having been modulatedbased on the conversion table.

FIG. 1 is a block diagram showing an example configuration of a knownmodulation apparatus.

As shown in FIG. 1, a modulation apparatus 10 includes a DSV-control-bitinserting unit 11 for inserting “1” or “0” as DSV control bits at apredetermined interval.

In the DSV-control-bit inserting unit 11, a data sequence in which a DSVcontrol bit “1” is to be inserted and a data sequence in which a DSVcontrol bit “0” is to be inserted are prepared. Furthermore, theDSV-control-bit inserting unit 11 adjusts the positions of DSV segmentsso that the channel-bit sequence of each DSV segment is obtained byconverting an input bit sequence including one DSV control bit.

A modulation unit 12 modulates the data sequences including DSV controlbits that have been inserted by the DSV-control-bit inserting unit 11. ADSV control unit 13 NRZI-modulates the code sequences having beenmodulated by the modulation unit 12, thereby obtaining level data, thencalculates DSVs, and finally outputs a recording code sequence for whichDSV control has been exercised.

As another example, Japanese Unexamined Patent Application PublicationNo. 11-346154, filed earlier by the applicant of this application,discloses a conversion table having, as conversion codes, base codeswith d=1, k=7, m=2, and n=3, a conversion rule such that the number of“1”s in an element of data sequences modulo two and the number of “1”sin a corresponding codeword sequence modulo two are coincidentally oneor zero, a first replacement code for restricting successive occurrencesof the minimum run d within a predetermined number of times, and asecond replacement code for complying with a run-length constraint.

FIG. 2 is a block diagram showing another example configuration of aknown modulation apparatus.

As shown in FIG. 2, a modulation apparatus 20 includes a DSV-control-bitdetermining and inserting unit 21 for determining “1” or “0” as a DSVcontrol bit and inserting it in an input data sequence at an arbitraryinterval; a modulation unit 22 for modulating the data sequenceincluding DSV control bits inserted; and an NRZI modulation unit 23 forconverting an output of the modulation unit 22 into a recording waveformsequence. Furthermore, the modulation apparatus 20 includes a timingmanagement unit 24 for generating a timing signal and supplying thetiming signal to each component to exercise timing management.

However, when implementing DSV control by the method described above,specific control signals or the like must be devised.

For example, in the method described above, in order to prevent achannel-bit sequence from being generated by conversion including a nextDSV control bit existing outside a relevant segment and to prevent anerror in a segment DSV value calculated, processing for shifting DSVsegments is executed. In order to implement such processing, controlsignals for controlling the operations of the components must bedevised.

Furthermore, for example, in the method described above, a register usedfor calculating a segment DSV value holds all the values used for aprevious calculation, sometimes causing an error in a segment DSV valuecalculated next due to unneeded values therein. Thus, in order toimplement such processing, control signals for controlling theoperations of the components and the components themselves must bedevised.

DISCLOSURE OF INVENTION

The present invention has been made in view of the situation describedabove, and an object thereof is to achieve a more suitable DSV controlby detecting a modulation delimiter and controlling a segment forcalculating a segment DSV value.

A modulation apparatus according to the present invention comprisesDSV-control-bit generating means for generating a DSV control bit thatis inserted in an input bit sequence in order to control a DSV of aparticular output code sequence; DSV-control-bit inserting means forinserting the DSV control bit generated by the DSV-control-bitgenerating means at a predetermined position of the input bit sequence;and first modulating means for modulating a post-insertion bit sequenceobtained by inserting the DSV control bit into the input bit sequence,into the channel-bit sequence based on a conversion rule of avariable-length code (d, k; m, n; r); wherein the DSV-control-bitgenerating means comprises modulation-delimiter detecting means fordetecting a modulation delimiter that serves as a delimiter forconversion of the variable-length code; and valid-delimiter detectingmeans for detecting a valid delimiter for controlling timing fordetermining a value of the DSV control bit, based on the modulationdelimiter detected by the modulation-delimiter detecting means.

The modulation apparatus may further comprise NRZI modulating means forNRZI modulating the channel-bit sequence to generate the particularoutput code sequence.

The conversion rule may be such that the number of “1”s in one block ofthe input bit sequence or the post-insertion bit sequence modulo twocoincides with the number of “1”s in a corresponding one block of thechannel-bit sequence modulo two.

The conversion rule may be such that successive occurrences of a minimumrun d in the channel-bit sequence is restricted within a predeterminednumber of times.

The conversion rule may have a minimum run=1, a maximum run k=7, a basedata length before conversion m=2, and a base channel-bit length afterconversion n=3.

In the modulation apparatus, the modulation apparatus may receive inputof data having the base data length m within a period of outputting thechannel-bit sequence having the base channel-bit length n.

The modulation-delimiter detecting means may detect one or two points ofthe modulation delimiter based on a pattern of the conversion rule, fora single codeword conversion based on the conversion rule with aconstraint length r=4.

The DSV-control-bit generating means may further comprise firstpost-insertion-bit-sequence-candidate generating means for inserting afirst candidate bit for the DSV control bit at the predeterminedposition of the input bit sequence to generate a firstpost-insertion-bit-sequence candidate from the input bit sequence;second post-insertion-bit-sequence-candidate generating means forinserting a second candidate bit for the DSV control bit at thepredetermined position of the input bit sequence to generate a secondpost-insertion-bit-sequence candidate from the input bit sequence;second modulating means for modulating the first and secondpost-insertion-bit-sequence candidates based on a conversion rule thatis the same as the conversion rule mentioned earlier; DSV calculatingmeans for calculating DSV values based on first and secondchannel-bit-sequence candidates generated respectively by the secondmodulating means; and DSV-control-bit determining means for determiningeither the first or the second candidate bit as the DSV control bitbased on the DSV values calculated by the DSV calculating means.

The DSV-control-bit determining means may determine the DSV control bitat a timing based on the valid delimiter detected by the valid-delimiterdetecting means.

The DSV calculating means may comprise segment-DSV calculating means forcalculating a segment DSV value of a current DSV control segment foreach of the first and second channel-bit-sequence candidates;accumulated-DSV processing means for processing an accumulated DSV valuebased on a result of determination by the DSV-control-bit determiningmeans; and an adder for adding the segment DSV value to the accumulatedDSV value before the current DSV control segment to generate the DSVvalue.

Each of the first and second modulating means may comprise a minimumnumber of registers required for executing modulation based on theconversion rule.

Content of a predetermined register of the DSV-control-bit generatingmeans may be matched with content of a register of a candidatedetermined when a DSV control bit has been determined by theDSV-control-bit determining means.

The timing based on the valid delimiter may be controlled so that aninput bit sequence of a segment for calculating the segment DSV includesonly one DSV control bit inserted at a predetermined position.

The modulation apparatus may further comprise firstsynchronization-signal inserting means for inserting a synchronizationpattern including a preset unique pattern into the channel-bit sequencegenerated, wherein the DSV-control-bit generating means furthercomprises second synchronization-signal inserting means for inserting apattern that is the same as the synchronization pattern into each offirst and second channel-bit-sequence candidates obtained by modulationby the second modulating means, and providing the DSV calculating meanswith the first and second channel-bit-sequence candidates.

A modulation method according to the present invention comprises aDSV-control-bit generating step of generating a DSV control bit that isinserted in an input bit sequence in order to control a DSV of aparticular output code sequence; a DSV-control-bit inserting step ofinserting the DSV control bit generated in the DSV-control-bitgenerating step at a predetermined position of the input bit sequence;and a first modulating step of modulating a post-insertion bit sequenceobtained by inserting the DSV control bit into the input bit sequence,into the channel-bit sequence based on a conversion rule of avariable-length code (d, k; m, n; r); wherein the DSV-control-bitgenerating step comprises a modulation-delimiter detecting step ofdetecting a modulation delimiter that serves as a delimiter forconversion of the variable-length code; and a valid-delimiter detectingstep of detecting a valid delimiter for controlling timing fordetermining a value of the DSV control bit, based on the modulationdelimiter detected in the modulation-delimiter detecting step.

A program of a first recording medium according to the present inventioncomprises a DSV-control-bit generating step of generating a DSV controlbit that is inserted into an input bit sequence in order to control aDSV of a particular output code sequence; a DSV-control-bit insertingstep of inserting the DSV control bit generated in the DSV-control-bitgenerating step at a predetermined position of the input bit sequence;and a first modulating step of modulating a post-insertion bit sequenceobtained by inserting the DSV control bit into the input bit sequence,into the channel-bit sequence based on a conversion rule of avariable-length code (d, k; m, n; r); wherein the DSV-control-bitgenerating step comprises a modulation-delimiter detecting step ofdetecting a modulation delimiter that serves as a delimiter forconversion of the variable-length code; and a valid-delimiter detectingstep of detecting a valid delimiter for controlling timing fordetermining a value of the DSV control bit, based on the modulationdelimiter detected in the modulation-delimiter detecting step.

A first program allows a computer to execute a DSV-control-bitgenerating step of generating a DSV control bit that is inserted in aninput bit sequence in order to control a DSV of a particular output codesequence; a DSV-control-bit inserting step of inserting the DSV controlbit generated in the DSV-control-bit generating step at a predeterminedposition of the input bit sequence; and a first modulating step ofmodulating a post-insertion bit sequence obtained by inserting the DSVcontrol bit into the input bit sequence, into the channel-bit sequencebased on a conversion rule of a variable-length code (d, k; m, n; r);wherein the DSV-control-bit generating step comprises amodulation-delimiter detecting step of detecting a modulation delimiterthat serves as a delimiter for conversion of the variable-length code;and a valid-delimiter detecting step of detecting a valid delimiter forcontrolling timing for determining a value of the DSV control bit, basedon the modulation delimiter detected in the modulation-delimiterdetecting step.

A DSV-control-bit generating method according to the present inventioncomprises a first post-insertion-bit-sequence-candidate generating stepof inserting a first candidate bit for a DSV control bit at apredetermined position of an input bit sequence to generate a firstpost-insertion-bit-sequence candidate from the input bit sequence; asecond post-insertion-bit-sequence-candidate generating step ofinserting a second candidate bit for the DSV control bit at thepredetermined position of the input bit sequence to generate a secondpost-insertion-bit-sequence candidate from the input bit sequence; asecond modulating step of modulating the first and secondpost-insertion-bit-sequence candidates based on a conversion rule of avariable-length code (d, k; m, n; r); a modulation-delimiter detectingstep of detecting a modulation delimiter that serves as a delimiter forconversion of the variable-length code in the second modulating step; avalid-delimiter detecting step of detecting a valid delimiter forcontrolling timing fro determining a value of the DSV control bit, basedon the modulation delimiter detected in the modulation-delimiterdetecting step; a DSV calculating step of calculating DSV values basedon first and second channel-bit-sequence candidates generatedrespectively in the second modulating step; and a DSV-control-bitdetermining step of determining either the first or the second candidatebit as the DSV control bit based on the DSV values calculated in the DSVcalculating step, at the timing based on the valid delimiter detected inthe valid-delimiter detecting step.

A program of a second recording medium according to the presentinvention comprises a first post-insertion-bit-sequence-candidategenerating step of inserting a first candidate bit for a DSV control bitat a predetermined position of an input bit sequence to generate a firstpost-insertion-bit-sequence candidate from the input bit sequence; asecond post-insertion-bit-sequence-candidate generating step ofinserting a second candidate bit for the DSV control bit at thepredetermined position of the input bit sequence to generate a secondpost-insertion-bit-sequence candidate from the input bit sequence; asecond modulating step of modulating the first and secondpost-insertion-bit-sequence candidates based on a conversion rule of avariable-length code (d, k; m, n; r); a modulation-delimiter detectingstep of detecting a modulation delimiter that serves as a delimiter forconversion of the variable-length code in the second modulating step; avalid-delimiter detecting step of detecting a valid delimiter forcontrolling timing fro determining a value of the DSV control bit, basedon the modulation delimiter detected in the modulation-delimiterdetecting step; a DSV calculating step of calculating DSV values basedon first and second channel-bit-sequence candidates generatedrespectively in the second modulating step; and a DSV-control-bitdetermining step of determining either the first or the second candidatebit as the DSV control bit based on the DSV values calculated in the DSVcalculating step, at the timing based on the valid delimiter detected inthe valid-delimiter detecting step.

A second program according to the present invention allows a computer toexecute a first post-insertion-bit-sequence-candidate generating step ofinserting a first candidate bit for a DSV control bit at a predeterminedposition of an input bit sequence to generate a firstpost-insertion-bit-sequence candidate from the input bit sequence; asecond post-insertion-bit-sequence-candidate generating step ofinserting a second candidate bit for the DSV control bit at thepredetermined position of the input bit sequence to generate a secondpost-insertion-bit-sequence candidate from the input bit sequence; asecond modulating step of modulating the first and secondpost-insertion-bit-sequence candidates based on a conversion rule of avariable-length code (d, k; m, n; r); a modulation-delimiter detectingstep of detecting a modulation delimiter that serves as a delimiter forconversion of the variable-length code in the second modulating step; avalid-delimiter detecting step of detecting a valid delimiter forcontrolling timing fro determining a value of the DSV control bit, basedon the modulation delimiter detected in the modulation-delimiterdetecting step; a DSV calculating step of calculating DSV values basedon first and second channel-bit-sequence candidates generatedrespectively in the second modulating step; and a DSV-control-bitdetermining step of determining either the first or the second candidatebit as the DSV control bit based on the DSV values calculated in the DSVcalculating step, at the timing based on the valid delimiter detected inthe valid-delimiter detecting step.

According to the modulation apparatuses and methods, DSV-control-bitgenerating method, and programs, a DSV control bit having a valuedetermined is inserted at a predetermined position of an input datasequence, the input data sequence is converted into a codeword sequencebased on a conversion table, a modulation delimiter that serves as adelimiter for variable-length codeword conversion based on theconversion table is detected, timing for determining a value of the DSVcontrol bit is controlled, and the value of the relevant DSV control bitis determined.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an example configuration of a knownmodulation apparatus.

FIG. 2 is a block diagram showing another example configuration of aknown modulation apparatus.

FIG. 3 is a block diagram showing an example configuration of amodulation apparatus according to the present invention.

FIG. 4 is a diagram for explaining processing executed by the modulationapparatus shown in FIG. 3.

FIG. 5 is a schematic diagram showing the configuration of registersduring conversion of an input data sequence to a channel-bit sequence.

FIG. 6 is a block diagram showing a detailed example configuration of aDSV-control-bit determining unit 31 of the modulation apparatus.

FIG. 7 is a diagram showing a specific example of how a 1-7 PP dataconversion unit sets a flag at a modulation-delimiter position.

FIG. 8A is a diagram showing how a modulation-delimiter detecting unitdetects a modulation delimiter.

FIG. 8B is a diagram showing how a modulation-delimiter detecting unitdetects a modulation delimiter.

FIG. 9A is a diagram showing an example of how a valid-delimiterdetecting unit controls a valid-delimiter signal.

FIG. 9B is a diagram showing an example of how a valid-delimiterdetecting unit controls a valid-delimiter signal.

FIG. 10A is a diagram showing how a DSV-control-bit determining unitdetermines a swap timing.

FIG. 10B is a diagram showing how a DSV-control-bit determining unitdetermines a swap timing.

BEST MODE FOR CARRYING OUT THE INVENTION

Now, an embodiment of the present invention will be described.Hereinafter, for convenience of description, a sequence of ‘0’s and ‘1’sof data before conversion (a data sequence before conversion) will beexpressed in ( ), such as (000011), and a sequence of ‘0’s and ‘1’s of acode after conversion (a codeword sequence) will be expressed in such as“000100100”. Table 2 given below is an example of a conversion table forconverting data into codes according to the present invention. TABLE 21, 7PP_table (d, k; m, n; r) = (1, 7; 2, 3; 4) Data Code 11 *0* (Before0: * = 1, Before 1: * = 0) 10 001 01 010 0011 010 100 0010 010 000 0001000 100 000011 000 100 100 000001 010 100 100 00001000 000 100 100 10000001001 000 100 000 010 00001010 000 100 000 001 00001011 000 100 000101 00000000 010 100 100 100 00000001 010 100 000 010 00000010 010 100000 001 00000011 010 100 000 101 #110111-01  :      001 :101 010 101→001000 000      00000:000 010 101 (cbit replace)      0000t: --------------Termination table 00 000    0000 010 100    000010 000 100 000    000000010 000 000 --------------

The conversion table shown in Table 2 has a minimum run d=1, a maximumrun k=7, and a conversion ratio of data to corresponding channel bitsm:n=2:3. The table is a variable-length table with a maximum constraintlength r=4. The conversion table includes, as conversion codes, basecodes (codes for the data sequences (11) to (00000011)) that arenecessary for conversion, replacement codes (codes for the data sequence(110111)) that are not necessary for conversion but that allows moreefficient conversion, and a termination table including terminal codes(codes for data sequences (00), (0000), (000010), and (000000)) forterminating a code at an arbitrary position. Furthermore, asynchronization signal is defined in the conversion table.

Furthermore, in Table 2, an indeterminate code (a code including *) isincluded in an element of base codes. The indeterminate code isdetermined as “0” or “1” so as to comply with the minimum run d and themaximum run k, regardless of the codeword sequence immediately beforeand after the indeterminate code. That is, in Table 2, if a two-bit datasequence before conversion is (11), “1000” or “101” is selecteddepending on a codeword sequence immediately before the data sequence,and the data sequence is converted accordingly. That is, if one channelbit of the immediately preceding codeword sequence is “1”, the two-bitdata (11) is converted into a codeword “000” in order to comply with theminimum run d. On the other hand, if one channel bit of the immediatelypreceding codeword sequence is “0”, the data sequence is converted intoa codeword “101” in order to comply with the maximum run k.

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Furthermore, the conversion table shown in Table 2 includes replacementcodes for restricting successive occurrences of the minimum run. If adata sequence (110111) is immediately followed by a data sequence (01),(001), or (00000), or if a data sequence (110111) is immediatelyfollowed by a data sequence (0000) and is thereby terminated, the datasequence (110111) is replaced by a codeword “001000000”. If theimmediately following data sequence is none of the data sequences givenabove, the data sequence (110111) is encoded by the unit of two bits((11), (01), (11)), and is thereby converted into a codeword sequence“101010101” or “000010101”.

Furthermore, the conversion codes in Table 2 have a conversion rule suchthat the number of ‘1’s in an element of data sequences modulo two andthe number of ‘1’s in a corresponding element of codeword sequencesmodulo two are coincidentally one or zero (The corresponding elementsboth have an odd number of ‘1’s or an even number of ‘1’s). For example,of the conversion codes, an element (000001) of data sequencescorresponds to an element “010100100” of codeword sequences. The numbersof ‘1’s in the respective elements are one for the data sequence andthree for the corresponding codeword sequence, and both arecoincidentally one modulo two (odd numbers). Similarly, of theconversion codes, an element (00000000) of data sequences corresponds toan element “010100100100” of codeword sequences. The numbers of ‘1’s inthe respective elements are zero for the data sequence and four for thecorresponding codeword sequence, and both are coincidently zero modulotwo (even numbers).

Referring next to FIG. 3, a modulation apparatus according to anembodiment of the present invention will be described with reference tothe figure. In this embodiment, a data sequence is converted into avariable-length code (d, k; m, n; r)=(1, 7; 2, 3; 4) according to Table2.

As shown in FIG. 3, a modulation apparatus 30 includes a DSV-control-bitdetermining unit 31 for determining ‘1’ or ‘0’, based on an input datasequence, as a DSV control bit to be inserted into the data sequence; aDSV-control-bit specified-position inserting unit 32 for inserting theDSV control bit having the value determined into the input data sequenceat an appropriate timing; a data conversion unit 33 for converting thedata sequence including the DSV control bit determined into channel bitsbased on a predetermined conversion table; a synchronization-signalinserting unit 34 for inserting a predetermined synchronization signalat a predetermined position of the channel bit sequence supplied fromthe data conversion unit 33; and an NRZI modulation unit 35 forconverting an output of the synchronization-signal inserting unit 34into a recording waveform sequence or a transmission code sequence.Furthermore, the modulation apparatus 30 includes a timing managementunit 36 for generating a timing signal and supplying the timing signalto the DSV-control-bit determining unit 31, the DSV-control-bitspecified-position inserting unit 32, the data conversion unit 33, thesynchronization-signal inserting unit 34, and the NRZI modulation unit35, thereby exercising timing management.

The timing of processing by the DSV-control-bit specified-positioninserting unit 32 has been described with reference to FIG. 3 as managedby the timing management unit 36. However, without limitation to thearrangement described above, for example, the DSV-control-bitspecified-position inserting unit 32 may further has the function ofadjusting timing of transmission of an input bit sequence, allowing aDSV control bit supplied from the DSV-control-bit determining unit 31 tobe inserted at a predetermined position of the input bit sequence whosetiming of transmission has been adjusted.

FIG. 4 is a diagram for explaining processing executed by the modulationapparatus 30 shown in FIG. 3. A data sequence includes information datasuch as an ECC (error correcting code) in addition to user data. TheDSV-control-bit specified-position inserting unit 32, based ondetermination by the DSV-control-bit determining unit 31, inserts DSVcontrol bits x1, x2, and x3 in the data sequence at a cycle of DSVsegments constituting DSV calculation intervals at arbitrary intervals.In FIG. 4, DSV segments correspond to DATA1, DATA2, and DATA3 havingarbitrary lengths.

In DATA1, a frame synchronization signal (hereinafter referred to as FS(frame sync)) for establishing synchronization between frames isinserted. Thus, DATA1, i.e., a DSV segment that serves as an interval ofinsertion of a DSV control bit, is set to be short.

That is, the length of DATA1 is determined so that span1 representingthe length of a DSV segment of a channel-bit sequence including channelbits Cbit1 corresponding to DATA1, span2 representing the length of aDSV segment of a channel-bit sequence including channel bits Cbit2corresponding to DATA2, and span3 representing the length of a DSVsegment of a channel-bit sequence including channel bits Cbit3corresponding to DAT43 will all be the same (span1=span2=span3).

Thus, if the FS inserted has FS (bits) and DATA2 and DATA3 both have x(bits), since the conversion ratio of the conversion table is m:n=2:3,DATA1 has x−FS*2/3 (bits). The DSV control bits each become longer inaccordance with the conversion ratio by the conversion into channel-bitsequences; that is, x1 is converted into Cx1, x2 is converted into Cx2,and x3 is converted into Cx3.

In order to accurately control the values of DSV control bits inserted,as will be described later, segments DSVspan1, DSVspan2, and DSVspan3are segmented ahead of positions where DSV control bits are actuallyinserted. At this time, only one DSV control bit is inserted in each ofthe segments.

As described above, a channel bit sequence (a recording code sequence ora transmission code sequence after NRZI modulation), after insertion ofFS, includes DSV control bits inserted at a regular interval, wherebyDSV control is exercised.

FIG. 5 is a schematic diagram showing the configuration of registersduring conversion of an input data sequence into a channel-bit sequence.FIG. 5 shows the configuration of registers that are at least requiredwhen converting a data sequence into a channel-bit sequence based onTable 2 given earlier. The registers include 12 bits of data[0:11] forstoring a data sequence including a DSV control bit inserted beforeconversion, and 18 bits of cbit[0:17] for storing a channel-bit sequenceafter conversion by the data conversion unit 33. Furthermore, a timingregister, etc. is provided.

FIG. 6 is a block diagram showing a specific example configuration ofthe DSV-control-bit determining unit 31 of the modulation apparatus 30.Referring to FIG. 6, a data sequence is supplied to the DSV-control-bitdetermining unit 31 and the DSV-control-bit specified-position insertingunit 32.

The DSV-control-bit determining unit 31 performs data conversion and DSVcalculation in two lines. A line for processing a data sequence with aDSV control bit having a value of ‘0’ and a line for processing a datasequence with a DSV control bit having a value of ‘1’ operateindependently of each other. That is, the data sequence supplied to theDSV-control-bit determining unit 31 is supplied to a DSV-control-bit-0adding unit 51 for adding a DSV control bit with a value of ‘0’ to theinput data sequence at a predetermined interval, and to aDSV-control-bit-1 adding unit 71 for adding a DSV control bit with avalue of ‘1’ to the input data sequence at a predetermined interval.

The data sequence with the DSV control bit having the value of ‘0’ addedthereto by the DSV-control-bit-0 adding unit 51 is supplied to a 1-7 PPdata conversion unit 52. The 1-7 PP data conversion unit 52 converts thedata sequence with the DSV control bit added thereto into a channel-bitsequence based on the conversion table shown in Table 2, havingparameters of (d, k; m, n; r)=(1, 7; 2, 3; 4), and supplies thechannel-bit sequence to a synchronization-signal inserting unit 53.

The synchronization-signal inserting unit 53 inserts a synchronizationsignal including a unique pattern that does not exist as a conversioncode of the conversion table, at a predetermined position of thechannel-bit sequence supplied from the 1-7 PP conversion unit 52, andsupplies the result to an NRZI modulation unit 54.

In order to allow the synchronization-signal inserting unit 53 to insertthe synchronization signal into the channel bit sequence, the 1-7 PPdata conversion unit 52 terminates conversion at an arbitrary positionof the data sequence based on the termination table shown in Table 2.The synchronization-signal inserting unit 53 inserts the synchronizationsignal subsequently to the terminating position of the channel-bitsequence.

The synchronization-signal inserting unit 53, having inserted thesynchronization signal in the channel-bit sequence, supplies informationof the last bit of the synchronization signal to the 1-7 PP dataconversion unit 52. The 1-7 PP data conversion unit, as required, refersto the information of the last bit of the synchronization signal toconvert the data sequence based on the conversion table shown in Table2.

The NRZI modulation unit 54 NRZI-modulates the channel bit sequenceincluding the synchronization signal, supplied from thesynchronization-signal inserting unit 53, and supplies the result to asegment-DSV calculating unit 55.

The segment-DSV calculating unit 55 calculates a segment DSV valuedetermined by DSV values in a particular DSV segment from theNRZI-modulated channel-bit sequence. In the calculation, the DSV valueis considered to be ‘+1’ if the value of an NRZI-modulated channel bitis ‘1’ and to be ‘−1’ if the value is ‘0’. The segment DSV valuecalculated is supplied to an adder 56.

The adder 56 adds an accumulated DSV value supplied from anaccumulated-DSV processing unit 61 to the segment DSV value suppliedfrom the segment-DSV calculating unit 55, as will be described later,and supplies the resulting new accumulated DSV value to theDSV-control-bit determining unit.

The accumulated DSV processing unit 61 stores in advance an accumulatedDSV value obtained by adding or subtracting all the segment-DSV valuesthat have been calculated. The accumulated-DSV processing unit 61supplies the accumulated DSV value stored therein to the adder 56 at apredetermined timing.

The 1-7 PP data conversion unit 52 supplies, to a modulation-delimiterdetecting unit 81, modulation-delimiter information for the datasequence including the DSV control bits, including information regardingmodulation delimiters based on the conversion table shown in Table 2.Furthermore, the 1-7 PP data conversion unit 52 supplies, to avalid-delimiter detecting unit 82, a DSV-segment-delimiter signal forthe data sequence including the DSV control bits, including informationregarding delimiter positions of DSV segments.

The modulation-delimiter detecting unit 81 detects modulation-delimiterpositions based on the modulation-delimiter information suppliedthereto. The modulation-delimiter detecting unit 81, having detected themodulation-delimiter positions, supplies a modulation-delimiter signalincluding information regarding the modulation-delimiter positions tothe valid-delimiter detecting unit 82.

The valid-delimiter detecting unit 82, based on theDSV-segment-delimiter signal representing the delimiter position of theDSV segment, supplied from the 1-7 PP data conversion unit 52, detects avalid-delimiter position for controlling the timing of determination ofa DSV control bit of the relevant DSV segment from themodulation-delimiter positions represented by the modulation-delimitersignal supplied from the modulation-delimiter detecting unit 81, andsupplies a valid-delimiter signal representing the valid-delimiterposition to the segment-DSV calculating unit 55 and the DSV-control bitdetermining unit 62.

The system for inserting DSV control bits having a value of ‘0’ in aninput data sequence is configured as described above. Also, the systemfor inserting DSV control bits having a value of ‘1’ is similarlyconfigured. That is, a DSV-control-bit-1 adding unit 71 corresponds tothe DSV-control-bit-0 adding unit 51, a 1-7 PP data conversion unit 72corresponds to the 1-7 PP data conversion unit 52, asynchronization-signal inserting unit 73 corresponds to thesynchronization-signal inserting unit 53, an NRZI modulation unit 74corresponds to the NRZI modulation unit 54, a segment-DSV calculatingunit 75 corresponds to the segment-DSV calculating unit 55, an adder 76corresponds to the adder 56, a modulation-delimiter detecting unit 91corresponds to the modulation-delimiter detecting unit 81, and avalid-delimiter detecting unit 92 corresponds to the valid-delimiterdetecting unit 82, and the components executes basically the sameprocessing, respectively.

The DSV-control-bit determining unit 62 receives, from the adder 56, anaccumulated DSV value that is based on the data sequence including DSVcontrol bits having the value of ‘0’, and also receives, from the adder76, an accumulated DSV value that is based on the data sequenceincluding the DSV control bits having the value of ‘1’. TheDSV-control-bit determining unit 62, based on these two accumulated DSVvalues, determines a value of DSV control bit to be inserted in the datasequence. That is, the DSV-control-bit determining unit 62 selects onewith a smaller absolute value of the two.

The accumulated DSV value determined by the DSV-control-bit determiningunit 62 as the value of the DSV control bit to be inserted in the datasequence is supplied to the accumulated-DSV processing unit 61. Theaccumulated-DSV processing unit 61, based on the DSV value suppliedthereto, updates an accumulated DSV value stored therein.

The DSV-control-bit determining unit 62, having determined the value ofthe DSV control bit to be inserted into the data sequence, supplies theresult of determination to the DSV-control-bit specified-positioninserting unit 32. The DSV-control-bit specified-position inserting unit32, based on the result of determination supplied from theDSV-control-bit determining unit 62, inserts the DSV control bit at apredetermined position of the data sequence, and supplies the result tothe data conversion unit 33.

Furthermore, the DSV-control-bit determining unit 62 suppliesinformation identifying which has been determined as the value of theDSV control bit to be inserted into the data sequence to the 1-7 PP dataconversion unit 52, the synchronization-signal inserting unit 53, theNRZI modulation unit 54, the segment-DSV calculating unit 55, the 1-7 PPdata conversion unit 72, the synchronization-signal inserting unit 73,the NRZI modulation unit 74, and the segment-DSV calculating unit 75,and updates, as required, the content of registers referred to by thecomponents.

That is, the values of the registers referred to by the components ofthe line associated with the determined value of the DSV control bit tobe inserted into the data sequence are correspondingly stored as valuesof registers referred to by the components of the opposite line.Consequently, the content of the registers referred to by the line foradding DSV control bits with a value of ‘0’ and the content of theregisters referred to by the line for adding DSV control bits with avalue of ‘1’ are matched with each other using the values of theregisters referred to by the line associated with the selected value ofthe DSV control bit.

The DSV-control-bit determining unit 31 for determining a value of a DSVcontrol bit to be inserted into the data sequence is configured asdescribed above.

Next, the operation of this embodiment will be described.

First, an input data sequence is supplied to the DSV-control-bit-0adding unit 51 and the DSV-control-bit-1 adding unit 71 of theDSV-control-bit determining unit 31 and to the DSV-control-bitspecified-position inserting unit 32.

The DSV-control-bit-0 adding unit 51, having received the data sequence,adds a DSV control bit having a value of ‘0’ to the data sequence at apredetermined interval. The 1-7 PP data conversion unit 52 obtains thedata sequence including the DSV control bits having the value of ‘0’,added by the DSV-control-bit-0 adding unit 51, and converts the datasequence into a channel-bit sequence composed of codewords based on theconversion table shown in Table 2.

The 1-7 PP data conversion unit 52, as required, refers to theinformation regarding the last bit of the synchronization signalsupplied from the synchronization-signal inserting unit 53 to convertthe data sequence into a channel-bit sequence. The channel-bit sequenceobtained by the conversion is supplied to the synchronization-signalinserting unit 53. Furthermore, the 1-7 PP data conversion unit 52, whenmodulating data, supplies modulation-delimiter-position information inwhich a flag is set at a modulation-delimiter position to themodulation-delimiter-position detecting unit 81, and supplies aDSV-segment-delimiter signal to the valid-delimiter detecting unit 82.

The synchronization-signal inserting unit 53, having received thechannel-bit sequence obtained by the conversion, inserts asynchronization signal having a predetermined pattern at a predeterminedposition of the channel-bit sequence, and supplies the result to theNRZI modulation unit 54. Furthermore, the synchronization-signalinserting unit 53 supplies the information regarding the last bit of thesynchronization signal to the 1-7 PP data conversion unit 52 so that the1-7 PP data conversion unit 52 can refer to the value of the last bit ofthe immediately preceding channel-bit sequence during data modulation.

Then, the NRZI modulation unit 54 NRZI-modulates the channel-bitsequence including the synchronization signal inserted by thesynchronization-signal inserting unit 53, and supplies the result to thesegment-DSV calculating unit 55.

The modulation-delimiter detecting unit 81, having received themodulation-delimiter-position information from the 1-7 PP dataconversion unit 52, detects modulation-delimiter positions, generates amodulation-delimiter-position signal, and supplies themodulation-delimiter position signal to the valid-delimiter detectingunit 82.

On the other hand, the DSV-control-bit-1 adding unit 71, having receiveda data sequence, adds DSV control bits having a value of ‘1’ to the datasequence at a predetermined interval. The 1-7 PP data conversion unit72, similarly to the 1-7 PP data conversion unit 52, converts the datasequence including the DSV control bits added thereto into a channel-bitsequence.

Furthermore, the 1-7 PP data conversion unit 72, as required, refers tothe information regarding the last bit of the synchronization signalsupplied from the synchronization-signal inserting unit 73 to convertthe data sequence into a channel-bit sequence. The channel-bit sequenceobtained by the conversion is supplied to the synchronization-signalinserting unit 73. Furthermore, the 1-7 PP data conversion unit 72supplies modulation-delimiter-position information to themodulation-delimiter-position detecting unit 91, and supplies aDSV-segment-delimiter signal to the valid-delimiter detecting unit 92.

The synchronization-signal inserting unit 73 inserts a synchronizationsignal, and supplies the result to the NRZI modulation unit 74.Furthermore, the synchronization-signal inserting unit 73 suppliesinformation regarding the value of the last bit of the synchronizationsignal to the 1-7 PP data conversion unit 72. Then, the NRZI modulationunit 74 NRZI-modulates the channel-bit sequence including thesynchronization signal inserted by the synchronization-signal insertingunit 73, and supplies the result to the segment-DSV calculating unit 75.

The modulation-delimiter detecting unit 91, having received themodulation-delimiter-position information from the 1-7 PP dataconversion unit 72, detects modulation-delimiter positions, generates amodulation-delimiter-position signal, and supplies themodulation-delimiter-position signal to the valid-delimiter detectingunit 92.

FIG. 7 is a diagram showing a specific example of how a 1-7 PP dataconversion unit sets a flag at a modulation-delimiter position.

Referring to FIG. 7, a data sequence with a control bit is sequentiallyinput to 12 bits of data[0:11] from data[0], and is shifted clock byclock toward the larger register number. Data that has been shifted todata[11] is discarded at the time of a next shift. The relationshipbetween the data sequence and a corresponding channel-bit sequence isshown in FIG. 5.

Although not shown in FIG. 5, a register for controlling timing, such asa register indicating modulation-delimiter positions, is configured soas to allow the same number of data to be stored as the register forstoring a channel-bit sequence, and the positions of these registerscorrespond to each other. In the register for timing control, forexample, “1” is stored for active, and ‘0’ is stored at the otherpositions.

A data sequence is processed by the unit of two data. If data [0, 1]=[1,1], data [0, 1]=[0, 1], or data [0, 1]=[1, 0], the 1-7 PP dataconversion unit 52, having detected (11), (10), or (01), determines aconversion pattern based on the conversion table shown in Table 2, asdescribed earlier. Then, a channel-bit sequence obtained by theconversion is stored in cbit[0, 1, 2]. At this time, 1 is stored in aregister representing a modulation-delimiter position corresponding tocbit[2].

If data [0, 1]=[0, 0], a conversion pattern is not determined with aconstraint length r=1, so that a new data sequence is sequentiallyinput. When two data have been newly input (four data in total), the 1-7PP data conversion unit 52 refers to data [0, 1, 2, 3]. If data [0, 1,2, 3]=[1, 1, 0, 0], data [0, 1, 2, 3]=[0, 1, 0, 0], or data [0, 1, 2,3]=[1, 0, 0, 0], the 1-7 PP data conversion unit 52, having detected(0011), (0010), or (0001), determines a conversion pattern based on theconversion table shown in Table 2, as described earlier. Then, achannel-bit sequence obtained by the conversion is stored in cbit[0, 1,2, 3, 4, 5]. At this time, 1 is stored in a register representing amodulation-delimiter position corresponding to cbit[5].

If data [0, 1, 2, 3]=[0, 0, 0, 0], a conversion pattern is notdetermined with a constraint length r=2, so that a new data sequence issequentially input. When two data have been newly input (six data intotal), the 1-7 PP data conversion unit 52 refers to data [0, 1, 2, 3,4, 5]. If data [0, 1, 2, 3, 4, 5]=[1, 1, 0, 0, 0, 0] or data [0, 1, 2,3, 4, 5]=[1, 0, 0, 0, 0, 0], the 1-7 PP data conversion unit 52, havingdetected (000011) or (000001), determines a conversion pattern based onthe conversion table shown in Table 2, as described earlier. Then, achannel-bit sequence obtained by the conversion is stored in cbit[0, 1,2, 3, 4, 5, 6, 7, 8]. At this time, 1 is stored in a registerrepresenting a modulation-delimiter position corresponding to cbit[8].

If data [0, 1, 2, 3, 4, 5]=[0, 0, 0, 0, 0, 0] or data [0, 1, 2, 3, 4,5]=[0, 1, 0, 0, 0, 0], a conversion pattern is not determined with aconstraint length of r=3, so that a new data sequence is sequentiallyinput. When two data have been newly input (eight data in total), the1-7 PP data conversion unit 52 refers to data [0, 1, 2, 3, 4, 5, 6, 7]to determine a conversion pattern based on the conversion table shown inTable 2, as described earlier.

More specifically, if data [0, 1, 2, 3, 4, 5, 6, 7]=[0, 0, 0, 0, 0, 0,0, 0], data [0, 1, 2, 3, 4, 5, 6, 7]=[1, 0, 0, 0, 0, 0, 0, 0], data [0,1, 2, 3, 4, 5, 6, 7]=[0, 1, 0, 0, 0, 0, 0, 0], data [0, 1, 2, 3, 4, 5,6, 7]=[1, 1, 0, 0, 0, 0, 0, 0], data [0, 1, 2, 3, 4, 5, 6, 7]=[0, 0, 0,1, 0, 0, 0, 0], data [0, 1, 2, 3, 4, 5, 6, 7]=[1, 0, 0, 1, 0, 0, 0, 0],data [0, 1, 2, 3, 4, 5, 6, 7]=[0, 1, 0, 1, 0, 0, 0, 0], or if data [0,1, 2, 3, 4, 5, 6, 7]=[1, 1, 0, 1, 0, 0, 0, 0], the 1-7 PP dataconversion unit 52, having detected (00000000), (00000001), (00000010),(00000011), (00001000), (00001001), (00001010), or (00001011), operatesas described earlier, using the conversion codes with a constraintlength r=4 in the conversion table shown in Table 2 to achieveconversion into “010100100100”, “010100000010”, “010100000001”,“010100000101”, “000100100100”, “000100000010”, “000100000001”, or“000100000101”. A channel-bit sequence obtained by the conversion isstored in cbit[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11]. At this time, 1 isstored in a register representing a modulation-delimiter position at aparticular position.

More specifically, if data [0, 1, 2, 3, 4, 5, 6, 7]=[0, 0, 0, 1, 0, 0,0, 0] or if data [0, 1, 2, 3, 4, 5, 6, 7]=[0, 0, 0, 0, 0, 0, 0, 0], asthe modulation-delimiter position, 1 is stored in a registerrepresenting a modulation-delimiter position corresponding to cbit[11]of cbit[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11].

Furthermore, if data [0, 1, 2, 3, 4, 5, 6, 7]=[1, 0, 0, 1, 0, 0, 0, 0],data [0, 1, 2, 3, 4, 5, 6, 7]=[0, 1, 0, 1, 0, 0, 0, 0], data [0, 1, 2,3, 4, 5, 6, 7]=[1, 1, 0, 1, 0, 0, 0, 0], data [0, 1, 2, 3, 4, 5, 6,7]=[1, 0, 0, 0, 0, 0, 0, 0], data [0, 1, 2, 3, 4, 5, 6, 7]=[0, 1, 0, 0,0, 0, 0, 0], or if data [0, 1, 2, 3, 4, 5, 6, 7]=[1, 1, 0, 0, 0, 0, 0,0], as the modulation-delimiter position, 1 is stored in registersrepresenting modulation-delimiter positions corresponding to cbit[11]and cbit[2] of cbit[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11].

In Table 2, conversion patterns not mentioned above exist in thetermination table. Operations for such conversion patterns are basicallythe same as the operations described above. That is, a conversionpattern is determined when a match is found in the termination tableshown in Table 2 and a position where a synchronization signal isinserted is detected. The modulation-delimiter position in this case isgiven at one point at the position of the last bit of channel bits foreach element determined.

As described above, all the patterns are converted from an input datasequence into a channel-bit sequence, and modulation-delimiterinformation is given. Then, a next pattern conversion starts again froma constraint length r=1 after a pattern has been determined andmodulation-delimiter information has been generated, and the operationdescribed above is repeated. At this time, the channel-bit sequence andthe modulation-delimiter information undergoes conversion before beingoutput by the 18-bit register shown in FIG. 5, and the channel-bitsequence and the modulation-delimiter information having undergoneconversion are supplied to the synchronization-signal inserting unit 53shown in FIG. 6.

Referring back to FIG. 6, the modulation-delimiter detecting unit 81refers to the register representing modulation-delimiter information todetect modulation-delimiter positions.

Similarly to the case described above, the modulation-delimiterdetecting unit 91 refers to the register representingmodulation-delimiter information to detect modulation-delimiterpositions. In this case, the processing executed by the 1-7 PP dataconversion unit 52 is executed by the 1-7 PP data conversion unit 72,and the processing executed by the synchronization-signal inserting unit53 is executed by the synchronization-signal inserting unit 73.

With regard to the relationship between an input data sequence and acorresponding codeword sequence, since the conversion ratio m:n is 2:3in this example, the amount of codeword data of 3 corresponds to theamount of data word data 2. Thus, of an input data sequence, onlyparticular two data words are input during two clock cycles, and theninput is stopped for one clock cycle. Thus, the deviation relating tothe conversion ratio between input data and output code is adjusted.This relationship is shown in data sequences and channel-bit sequencesshown in FIGS. 8A, 8B, 9A, 9B, 10A, and 10B.

FIGS. 8A and B are diagrams showing how the modulation-delimiterdetecting unit 81 shown in FIG. 6 detects a modulation delimiter. InFIGS. 8A and B, time elapses from left to right, and a data sequence issequentially input to the register from the left and converted into achannel-bit sequence.

Referring to FIG. 8A, a data sequence of two bits (11) is converted into“101”, and ‘1’ is stored at a position of the register representing amodulation delimiter, corresponding to “1” at the beginning of “101”. Asdescribed earlier, the modulation-delimiter detecting unit 81 refers tothe register to detect a modulation-delimiter position, and controls amodulation-delimiter signal.

A data sequence of eight bits (00000000) is converted into“010100100100”, and ‘1’ is stored at a position of the registerrepresenting a modulation delimiter, corresponding to “0” at thebeginning of “010100100100”. As described earlier, themodulation-delimiter detecting unit 81 refers to the register to detecta modulation-delimiter position, and controls a modulation-delimitersignal.

Similarly, a data sequence of four bits (0011) is converted into“010100”, and ‘1’ is stored at a position of the register representing amodulation delimiter, corresponding to “0” at the beginning of “010100”.As described earlier, the modulation-delimiter detecting unit 81 refersto the register to detect a modulation-delimiter position, and controlsa modulation-delimiter signal.

Similarly, referring to FIG. 8B, a two-bit data sequence (11) isconverted into “101”, and ‘1’ is stored at a position of the registerrepresenting a modulation delimiter, corresponding to the “1” at thebeginning of “101”. As described earlier, the modulation-delimiterdetecting unit 81 refers to the register to detect amodulation-delimiter position, and controls a modulation-delimitersignal.

A data sequence of eight bits (00000001) is converted into“010100000010”, and ‘1’ is stored at positions of the registerrepresenting modulation delimiters, corresponding to “0” at thebeginning of “010100000010” and “0” at the third position from the rightthereof. As described earlier, the modulation-delimiter detecting unit81 refers to the register to detect modulation-delimiter positions, andcontrols a modulation-delimiter signal.

Similarly, with regard to a data sequence of four bits (0011), ‘1’ isstored at a position of the register representing a modulationdelimiter, corresponding to “0” at the beginning of “010100”. Asdescribed earlier, the modulation-delimiter detecting unit 81 refers tothe register to detect a modulation-delimiter position, and controls amodulation-delimiter signal.

As described above, the number of modulation delimiters vary dependingon conversion patterns with a constraint length i=4.

The modulation-delimiter detecting unit 81 may integratemodulation-delimiter positions for pattern conversion with a constraintlength i=4, i.e., with eight data, into a foremost one point, and outputit as a modulation-delimiter signal. This also allows the operation ofthe DSV-control-bit determining unit 31. In this case, a differencearises in the results of calculation of the segment DSVs; however, thesame result can be obtained for the accumulated DSV.

The modulation-delimiter signal generated by the modulation-delimiterdetecting unit 81 is supplied to the valid-delimiter detecting unit 82.The valid-delimiter detecting unit 82, upon receiving themodulation-delimiter signal, detects a valid-delimiter position based ona DSV-segment-delimiter signal supplied from the 1-7 PP data conversionunit 52, and supplies a valid-delimiter signal to the segment-DSVcalculating unit 55 and the DSV-control-bit determining unit 62.

The modulation-delimiter detecting unit 91 operates similarly to themodulation-delimiter detecting unit 81. A modulation-delimiter signalgenerated by the modulation-delimiter detecting unit 91 is supplied tothe valid-delimiter detecting unit 92. The valid-delimiter detectingunit 92, upon receiving the modulation-delimiter signal, detects avalid-delimiter position based on a DSV-segment-delimiter signalsupplied from the 1-7 PP data conversion unit 72, and supplies avalid-delimiter signal to the segment-DSV calculating unit 75 and theDSV-control-bit determining unit 62.

FIGS. 9A and B are diagrams showing an example of how a valid-delimiterdetecting unit controls a valid-delimiter signal. In FIGS. 9A and B,time elapses from left to right, and a data sequence is sequentiallyinput to the register from the left and converted into a channel-bitsequence.

In FIGS. 9A and B, DSV control bits are inserted into a data sequence atan interval of 60 data. That is, a DSV control bit is inserted after asuccession of 59 data of the data sequence. Furthermore, aDSV-segment-delimiter position is controlled so as to be generated atthe position of 51st data (data sequence 50 in FIGS. 9A and B) in a DSVsegment of the 60th data. That is, a DSV-segment-delimiter-positionsignal is set such that a DSV-segment-delimiter position is given 9 dataahead of the position of a DSV control bit, considering that a datasequence is converted into a variable-length code based on the 1-7 PPconversion table.

Since the value of the DSV control bit is arbitrary, insertion of a DSVcontrol bit into a data sequence causes a difference in a channel-bitsequence obtained by the conversion. That is, a DSV value can becalculated more accurately if a next DSV control bit yet to bedetermined does not affect conversion of a data sequence in calculatinga segment DSV value of a segment controlled by a single DSV control bit.Thus, a DSV-segment-delimiter position is set at a position that isdifferent from an actual delimiter position in a DSV segment.

In the 1-7 PP conversion table shown in Table 2, the maximum size of adata sequence that is referred to for a single modulating operation iseleven data (11011100000). Furthermore, it is ensured only forconversion up to 49th data that conversion takes place by the unit oftwo data and that a data sequence is converted not including a DSVcontrol bit of a next DSV segment (the data sequence is not affected bya next DSV control bit). As for conversion of the subsequent 51st data,the maximum data sequence that is referred to for a single modulatingoperation includes a DSV control bit of a next DSV segment. Thus, theposition of a DSV-segment delimiter in the DSV segment of the 60th datais set at the 51st data or later.

The DSV-segment-delimiter position is related to low-frequencysuppression characteristics. As the position is shifted backward, lowfrequencies are suppressed, desirably improving the performance of themodulating apparatus. From what has been described above, in FIGS. 9Aand B, a DSV-segment-delimiter position is set at the 51st data (datasequence 50 in FIGS. 9A and B).

Consequently, in a DSV segment of a DSV-block-delimiter-position signal,only one DSV control bit is inserted.

In FIG. 9A, the DSV segment is 60 data, and a DSV control bit having avalue of ‘0’ is inserted in the 60th data. Furthermore, the datasequence is composed of ‘0’s only, and (00000000) is repeatedlyconverted into “010100100100”. The six data at the beginning, togetherwith the preceding two data (00) not shown, is treated as (00000000) forconversion. At this time, a DSV control bit is included in the nextconversion unit consisting of eight data (00000000).

As described earlier, in the case of (00000000), only one modulationdelimiter is provided, at the beginning of the pattern. That is, in thecase of FIG. 9A, modulation delimiters are provided at the 55th data(data sequence 54 in FIGS. 9A and B) and the 3rd data in the next DSVsegment (data sequence 2 in FIGS. 9A and B). Thus, themodulation-delimiter detecting unit 81 supplies, to the valid-delimiterdetecting unit 82, a modulation-delimiter signal that is controlled suchthat the 55th data and the 3rd data of the next DSV segment are ‘1’.

Since the DSV-segment-delimiter position is at the 51st data asdescribed earlier, the 1-7 PP data conversion unit 52 supplies, to thevalid-delimiter detecting unit 82, a DSV-segment-delimiter signal havinga value of ‘1’ at and subsequently to the 51st data (data sequence 50 inFIGS. 9A and B). The value of the DSV-segment-delimiter signal isreturned to ‘0’ when the segment-DSV-control processing has beencompleted. For example, as shown in FIG. 9A, the DSV-segment-delimitersignal is returned to ‘0’ at each 1st data (data sequence 0 in FIGS. 9Aand B).

The valid-delimiter detecting unit 82, based on the modulation-delimitersignal and the DSV-segment-delimiter signal supplied thereto, detectsthe 55th data (data sequence 54 in FIGS. 9A and B), which is the firstmodulation delimiter that occurs after the DSV-delimiter positionbecomes ‘1’, as a valid delimiter. The valid-delimiter detecting unit 82then generates a valid-delimiter signal that is controlled such that the55th data is ‘1’, and supplies the valid-delimiter signal to thesegment-DSV calculating unit 55 and the DSV-control-bit determining unit62.

On the other hand, FIG. 9B is a diagram showing how theDSV-control-bit-1 adding unit 71 inserts a DSV control bit having avalue of ‘1’ at the 60th data while leaving other data ‘0’. The fourdata at the beginning, together with the preceding four data (0000) notshown, are treated as (00000000) for conversion.

At this time, a DSV control bit is included in the next conversion unitconsisting of eight data (00000001).

(00000001), which includes a DSV control bit, is converted into“010100000010”. In this case, as described earlier, modulationdelimiters are provided at two points, at the 53rd data (data sequence52 in FIGS. 9A and B) and the 59th data (data sequence 58 in FIGS. 9Aand B).

In the case of FIG. 9B, the modulation-delimiter position differs fromthat in the case of FIG. 9A. Usually, when a random pattern is input, adata sequence with a DSV control bit having a value of ‘0’ and a datasequence with a DSV control bit having a value of ‘1’ converge as timeelapses, and modulation-delimiter positions match in the proximity ofmodulation delimiters. However, in the case of a particular pattern,sometimes, conversion does not occur as in the above example, andmodulation-delimiter positions do not match even in the proximity ofmodulation delimiters, affecting DSV segments.

Even in that case, the valid-delimiter detecting units 82 and 92 outputvalid-delimiter signals with a mutual deviation as they are, as in thenormal case.

In FIGS. 9A and B, DSV segments are shown without consideration of adelay associated with the registers shown in FIG. 5. However, withoutlimitation to the above arrangement, for example, DSV segments may becounted at the register cbit[0] for storing a channel-bit sequence,shown in FIG. 5, referring to a data sequence, a channel-bit sequence,and modulation-delimiter information at cbit[17]. In that case, the datasequence, the channel-bit sequence, and the modulation-delimiterinformation that are referred to are delayed by 18 bits relative to thecounter of DSV segments, as shown in FIG. 5. However, thevalid-delimiter detecting units 82 and 92 detect valid delimiterssimilarly to the example described above.

As described above, based on the timing of the valid delimiter detected,the segment-DSV calculating unit 55 calculates a segment-DSV value fromthe channel-bit sequence of the relevant DSV segment, and supplies thesegment-DSV value to the adder 56. Similarly, the segment-DSVcalculating unit 75 calculates a segment DSV value, and supplies thesegment-DSV value to the adder 76 based on the timing of the validdelimiter detected.

The adder 56 adds an accumulated DSV value supplied from theaccumulated-DSV processing unit 61 to the segment-DSV value suppliedthereto, and supplies an accumulated-DSV value newly calculated to theDSV-control-bit determining unit 62. Similarly, the adder 76 adds anaccumulated DSV value supplied from the accumulated-DSV processing unit61 to the segment-DSV value supplied thereto, and supplies anaccumulated-DSV value newly calculated to the DSV-control-bitdetermining unit 62.

The DSV-control-bit determining unit 62, having received these two newDSV values, determines a value of a DSV control bit to be inserted intothe data sequence based on the timings of valid-delimiter signalssupplied from the valid-delimiter detecting units 82 and 92. TheDSV-control-bit determining unit 62 selects, of the two newly calculatedaccumulated-DSV values supplied from the adders 56 and 76, one with asmaller absolute value. The DSV-control-bit determining unit 62, havingdetermined the value of the DSV control bit to be inserted, supplies theinformation to the DSV-control-bit specified-position inserting unit 32,and supplies the new accumulated-DSV value selected to theaccumulated-DSV processing unit 61.

Furthermore, the DSV-control-bit determining unit 62 activates aswapping operation for controlling the values of registers that are usedfor calculation of a next DSV segment. That is, the DSV-control-bitdetermining unit 62 supplies information that specifies the selectedline to the 1-7 PP data conversion unit 52, the synchronization-signalinserting unit 53, the NRZI modulation unit 54, the segment-DSVcalculating unit 55, the 1-7 PP data conversion unit 72, thesynchronization-signal inserting unit 73, the NRZI modulation unit 74,and the segment-DSV calculating unit 75. Then, the values of theregisters referred to by the components of the selected line are storedin place of the values of the registers referred to by the components ofthe opposite line.

FIGS. 10A and B are diagrams showing how the DSV-control-bit determiningunit 62 determines a swap timing.

Referring to FIG. 10A, a valid-delimiter signal based on a data sequenceincluding a DSV control bit having a value of ‘0’ is supplied to theDSV-control-bit determining unit 62. The DSV-control-bit determiningunit 62, at a next timing of a valid delimiter, determines a DSV controlbit. Then, at a yet next timing, a swapping operation is executed,controlling the registers so that the contents of the registers arematched with the contents of the registers of the selected line.

Referring to FIG. 10B, a valid-delimiter signal based on a data sequenceincluding a DSV control bit having a value of ‘1’ is supplied to theDSV-control-bit determining unit 62. In the case of FIG. 10B, thevalid-delimiter position differs as compared with the case of FIG. 10A.In this case, the DSV-control-bit determining unit 62 determines a DSVcontrol bit at a timing next to occurrences of valid delimiters on bothlines. That is, in the case of FIGS. 10A and B, since thevalid-delimiter position is later in FIG. 10A than in FIG. 10B,determination is carried out at a timing next to the valid-delimiterposition in FIG. 10A.

Now, let it be supposed that the line associated with a DSV control bithaving a value of ‘0’ is selected. Then, the DSV-control-bit determiningunit 62 supplies the new accumulated-DSV value, supplied from the adder56, to the accumulated-DSV processing unit 61. Furthermore, theDSV-control-bit determining unit 62 supplies a result of determinationto the DSV-control-bit specified-position inserting unit 32, and also tothe 1-7 PP data conversion unit 52, the synchronization-signal insertingunit 53, the NRZI modulation unit 54, the segment-DSV calculating unit55, the 1-7 PP data conversion unit 72, the synchronization-signalinserting unit 73, the NRZI modulation unit 74, and the segment-DSVcalculating unit 75.

Then, the contents of the register of the 1-7 PP data conversion unit52, on the line associated with the selected value ‘0’ of the DSVcontrol bit, are stored in the 1-7 PP data conversion unit 72.Similarly, the contents of the register of the synchronization-signalinserting unit 53 are stored in the synchronization-signal insertingunit 73, the contents of the register of the NRZI modulation unit 54 arestored in the NRZI modulation unit 74, and the contents of the registerof the segment-DSV calculating unit 55 are stored in the segment-DSVcalculating unit 75. By the swapping operation described above, thecontinuity of data is maintained.

Although a case where the valid-delimiter positions differ is shown inFIGS. 10A and B, a similar operation is also executed in a case wherethe valid-delimiter positions are the same. That is, the DSV-control-bitdetermining unit 62 determines a DSV control bit at a timing next to thevalid delimiter. Then, the DSV-control-bit determining unit 62, at a yetnext timing, executes a swapping operation, controlling the registers sothat the contents will be matched with the contents of the registers ofthe selected line.

The example shown in FIGS. 10A and B has been described such that validdelimiters are detected without consideration of a delay associated withthe registers shown in FIG. 5. However, without limitation to theexample, a delay associated with the registers may be considered. Evenin that case, the DSV-control-bit determining unit 62 executes anoperation similar to that described above.

As described above, the DSV-control-bit determining unit 62, using thevalues of registers referred to by a line associated with a valueselected as a DSV control bit to be inserted into a data sequence,updates (swaps) the values of registers on the opposite line notselected, so that the values of these registers match. At this time, theDSV-control-bit determining unit 62 controls the swap timing so that ineach of the registers, a next DSV control bit or information including anext DSV control bit will not be stored.

The DSV-control-bit specified-position inserting unit 32, upon obtaininginformation regarding the value of the DSV control bit from theDSV-control-bit determining unit 62, inserts a DSV control bit havingthe specified value in the data sequence, and supplies the result to thedata conversion unit 33. The data conversion unit 33 converts the datasequence including the DSV control bit into a channel-bit sequence withreference to the conversion table shown in Table 2, and supplies theresult to the synchronization-signal inserting unit 34. Thesynchronization-signal inserting unit 34 inserts a predeterminedsynchronization signal in the channel-bit sequence, and supplies theresult to the NRZI modulation unit 35. The NRZI modulation unit 35converts the channel-bit sequence supplied thereto into a recording codesequence or a transmission code sequence, and outputs the code sequence.

The modulation apparatus 30 modulates an input data sequence in themanner described above. Thus, the modulation apparatus 30 is allowed todetermine a value of a DSV control bit to be inserted more accurately.

A providing medium for providing a user with a computer program forexecuting the processing described above may be a recording medium suchas an optical disc, a magneto-optical disc, a magnetic disc, a DVD-ROM,or a solid memory, or a communication medium such as a network or asatellite.

Industrial Applicability

As described above, according to a modulation apparatus and method, anda DSV-control-bit generating method of the present invention, a moresuitable DSV control is achieved by detecting a modulation delimiter andcontrolling a segment for calculation of a segment-DSV value.

1-17. (canceled)
 18. A digital sum value (DSV) control bit generatingmethod for generating a DSV control bit that is used for modulation inwhich a channel-bit sequence from an input bit sequence and generatingcode sequence from the channel-bit sequence generated, theDSV-control-bit generating method comprising: a firstpost-insertion-bit-sequence-candidate generating step of inserting afirst candidate bit for the DSV control bit at a predetermined positionof the input bit sequence to generate a firstpost-insertion-bit-sequence candidate from the input bit sequence; asecond post-insertion-bit-sequence-candidate generating step ofinserting a second candidate bit for the DSV control bit at thepredetermined position of the input bit sequence to generate a secondpost-insertion-bit-sequence candidate from the input bit sequence; amodulating step of modulating the first and secondpost-insertion-bit-sequence candidates based on a conversion rule of avariable-length code (d, k; m, n; r); a synchronization-signal insertingstep of inserting a synchronization signal including a unique pattern ata predetermined position into each of the modulated first and secondpost-insertion-bit-sequence candidates supplied from the modulatingstep, a modulation-delimiter detecting step of detecting a modulationdelimiter that serves as a delimiter for conversion of thevariable-length code in the modulating step; a valid-delimiter detectingstep of detecting a valid delimiter for controlling timing fordetermining a value of the DSV control bit, based on the modulationdelimiter detected in the modulation-delimiter detecting step; a DSVcalculating step of calculating DSV values based on first and secondchannel-bit-sequence candidates generated respectively in the modulatingstep; and a DSV-control-bit determining step of determining either thefirst or the second candidate bit as the DSV control bit based on theDSV values calculated in the DSV calculating step, at the timing basedon the valid delimiter detected in the valid-delimiter detecting step.